The subject of the present invention is a bias and precharging circuit for a bit line of EPROM memory cells in CMOS technology.
Known circuits of this type used for reading cells of an EPROM memory cell matrix comprise a part designed for bias of the bit line and a part designed for fast precharging of said bit line. There is also provided a sensing amplifier operating by comparison of the voltage of said bit line with that of a dummy bit line connected to comparison memory cells never subjected to programming.
Said circuits are based on the principle that bias originates in the bit line a voltage which depends on the state of conduction of the cell being read and is thus unbalanced with that of the dummy bit line. The unbalance is sensed by the sensing amplifier, which converts it into a reading signal indicating the state of the cell being read. Precharging makes reading fast.
The principal drawbacks of the abovesaid circuits are represented at present by high current consumption and the need for a very sensitive and hence rather complicated sensing amplifier which would be capabale of sensing a rather small voltage unbalance at its ends.